RAPID DEVELOPMENT METHODS

SUMMARY

This sub-theme aims to establish where in the system implementation design process opportunities for greater efficiency could be found. It will also establish whether processing functionality can be captured at a processing platform-independent level thereby avoiding the problems of rapid obsolescence in processor platforms.

MILITARY BENEFITS

A critical impediment to future system procurements will be affordability. Rapid development can help reduce the through life costs of an equipment and will help move potential capability from the design lab to the front line.

RESEARCH OBJECTIVE

To baseline current methods and determine the bottlenecks in existing development programmes.
To assess current tools to determine their relevance to modern military programmes.
To focus on areas where improvements to tools could produce significant benefits, in particular to assess platform-independent design methods.
In years 2 and 3 to produce tangible demonstrations of the improvements made in the tools.
To advance the concepts of virtual prototyping and platform-independent design from TRL1 to TRL3.

RESEARCH OUTLINE

This research will exploit the internal company processes of both BAE SYSTEMS and Roke Manor Research in order to rapidly baseline state-of-the-art design methods. Both companies have processes for rapid development, evolved over many programmes, the two organisations covering both military development programmes as well as rapid commercial developments (for Siemens mobile phone products). The programme will look at the complete development cycle from requirements capture, system modelling through to FPGA and DSP coding.

Example algorithms will be used as benchmarks by which different tools and methodologies may be compared. Particular emphasis will be given to the development of tools to support the rapidly increasing complexity/capability of parallel DSP and FPGA platforms.

In the latter stages of this project the strategies selected as “best of breed” will be tested against a real problem set and the robustness of the tools to the problems of platform changes, design requirement changes and technology updates will be demonstrated.

CO-ORDINATION WITH EXISTING / PREVIOUS RESEARCH

This research will make maximum use of internal funded programmes in this area. It will also endeavour to align itself with CRP programmes, in particular Nallatech are currently contracted to look at component obsolescence problems and the use of FPGAs to mitigate this. Subject to MOD approval this work will feed directly into this proposed activity.

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